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AN264/0289 and thermal characteristics of plastic smds by c. cognetti, e. stroppolo and r. tiziani resistance to soldering heat introduction surface mount technology (smt) has introduced a number of new technical problems, which have de- layed the conversion from insertion assembly. this is not strange : what readily available source of expertise existed a few years ago ? plastic so packages were introduced in europe in the early '70s and widely used in hybrids, but hybrid assembly has little relationship with the placement, soldering, handling tools now considered for sm pcb production. was it surprising that even the se- miconductor suppliers with sound experience in so production could not give all of the answers needed by the pcb manufacturer ? japanese experience in smt based consumer pro- ducts is impressive : 87% of components used for cameras are in sm versions. however, the degree of complexity and performance of consumer pro- ducts are somewhat different from the industrial, au- tomotive and telecoms applications the western world is interested in. on the other hand, in 1985 the percentageof smds (active and passive) usedin in- dustrial systems produced in japan was 16.6% in telephones, 5.5% in automotive applications, 5.1% in cable communication, 0.7% in minicomputers 1 ; that is, a level similar to us and european produc- tion, presumably with a similar level of expertise. in the past few years confidence in smt has increa- sed. more experience exists, which is the result of an expensive learning phase covered by both smd manufacturers and users. the reliability of plastic smds has an important pla- ce in this work. it needs a new approach in compa- rison with equivalent insertion devices, due to the completely different use. in 14 years of production, no distinction was made in the authors' company between so and dip, from the point of view of reliability. they had the same re- liability targets and similar evaluation methodology ; the former was often hot plate soldered on leaded ceramics for more convenient handling but no diffe- rence in long-term reliability existed. with smt, this is inadequate. negative effects due to the various assembly processes, and to some thermomechanical influence of the board, can limit the device life. the present work is focused on smds solderedonto a plastic substrate, by means of the most common industrial processes, and takes into account two aspects of reliability : 1. resistance to soldering heat, i.e., the suitability to withstand the thermal shock associated with the soldering cycle, without reducing reliability. this information is obtained by performing moisture resistance tests. data about so packages will be presented. for plccs, evaluation is in progress and will be concluded in the first half of 1988. 2. heat dissipation,which influences the failure rate. this information is obtained with test patterns and test boards designed by sgs-thomson microelectronics and includes thermal impedan- ce in pulsed conditions.a few case studieswill be included in this paper but complete charac- terisations are available elsewhere. 2 resistance to soldering heat in through-hole technology, devices are inserted from the upper side of the board and wave soldered from its lower side. only the lead extremities reach the temperature (250-260 c) of the molten solder ; the maximum specified soldering time of 10s is short enough to avoid over-heating of the package body, which ge- nerallydoes not exceed 120-130 cduring the whole process. this temperature is lower than the moulding com- pound glass transition temperature (160-170 c) and the risk of permanent damage to the package structure or to the silicon die is excluded. device reliability is defined almost independently of the soldering time and temperature ; devices under reliability test are mounted on sockets, thus neglec- ting the effect of the assembly process. on the contrary, in all industrial smt processes, de- vices are soldered in a high temperature ambient (215-260 c), with high heating rate, and the plastic package is kept in glass transition conditions application note 1/11
(figure 1) for a relatively long time (up to 60s). this situation was never encountered before. concern over reduced reliability is justified and ex- plains the trend towards defining smd reliability af- ter the soldering cycle, in order to include the effects summarised in table 1. figure 1 : thermal expansion of moulding com- pounds, compared with the tempera- ture of different soldering techniques. table 1 : factors affecting smd reliability on printed board. smd package design and structure internal contamination thermomechanical properties volume and thermal inertia water content lead solderability assembly process soldering method soldering time/temperature contamination level (flux) rinsing substrate thermomechanical properties thermal dissipation experimental reliability tests are performed on parts soldered onto test boards (4.5 in. x 6.5 in. fr-4 substrates). sm pcb1 test board can accept so-8, 14, 16. it is pre-grooved, in order to be cut in 35 positions, ha- ving the lay-out shown in figure 2 ; the smd foot- prints are electrically connected to through-holes, with a pitch of 100 mils and placed in two parallel rows, 600 mils apart. commercial pins inserted in the through-holes give the possibility of using the same equipment needed by dips. the soldering processes from table 2 were used for so packaged bipolar operational amplifiers and c- mos standard logic. in order to simulate a rework, the soldering cycle was repeatedon a number of de- vices. soldering is followed by the usual rinsing in water or freon, with or without ultrasonics. figure 2 : sm pcb1 test board. table 2 : soldering processes evaluated with so packaged devices. preheating soldering number of cycles double wave 120 c/30s 225 c/4s 1 double wave 120 c/30s 250 c/4s 1 double wave 110 c/30s 250 c/3.4s 1, 2, 3, 4 triple wave 110 c/30s 260 c/3s 1, 2, 3 vapour phase 215 c/20s 1, 2 infra-red 160 c/30s > 210 c/60s 1 the reliability evaluation was performed by means of the following tests : operating life 150 c pressure pot 121 c/2atm thb 85 c/85% rh 15v (bips) 6v (cmos) hast 130 c/85% rh 15v (bips) 6v (cmos) thermal cycles 55/+ 150 c (30/5/30 min) thermal shocks 55/+ 150 c (5/1/5 min liquid) 130 c/85%rh highly accelerated steam test (hast) has an acceleration factor of about 18-20 (ref. 3) in comparison with 85c/85%rh, and the concrete possibility of reaching wear-out exists with this test, after an acceptable time. for plcc packages a similar methodology is follo- wed. at the time of writing, only partial data are avai- lable, which will not be included here. application note 2/11
experimental results experimental results are summarised in tables 3-6. table 3 : cumulative reliability data after multiple wave soldering. test vehicles : lm2904 (so-8), lm2901 (so-14) and m74hc74 (so-14) double wave 225 c/4s 250 c/4s triple wave 260 c/3s operating life 1000h 0/154 0/32 pressure pot 96h 0/104 0/62 thb 85 c/85%rh 1000h 2000h 1/105* 0/32 0/32 hast 130 c/85%rh 100h 200h 0/64 0/64 thermal shocks 500 0/231 0/77 * parametric failure table 4 : reliability data after vapour phase reflow. test vehicle : lm2901 (so-14) 215 c/20s 215 c/40s operating life 1000h 0/32 pressure pot 96h 0/32 thb 85 c/85%rh 1000h 2000h 0/32 0/32 hast 130 c/85%rh v = 15v 100h 200h 372h 458h 635h 0/56 0/56 0/24 2/24 5/22 0/12 0/12 1/12 1/11 3/10 thermal cycles 500 0/32 all failures due to pad corrosion table 5 : cumulative reliability data after infra-red reflow. test vehicles : m74hc00 and m74hc74 (so-14) > 210 c/60s operating life 1300h 0/34 thb 85 c/85%rh 1300h 0/34 hast 130 c/85%rh 100h 200h 500h 672h 0/32 0/32 0/32 0/32 thermal cycles 750 0/70 table 6 : cumulative reliability data in multiple wave soldering with repetition of the soldering cycle. test vehicles : lm2903 (so-8), lm2901 and m74hc00 (so-14) double wave 250 c/3.4s triple wave 260 c/3s number of cycles 1 2 3 4 1 2 3 pressure pot 96h 504h 0/56 0/56 100 thermal cycles ( 40/150 c) followed by pressure pot 96h 168h 240h 0/30 0/30 0/30 0/30 0/30 0/30 0/60 0/60 0/60 hast 130 c/85%rh v=6v 100h 500h 1000h 1150h 1300h 0/32 0/32 0/32 0/18 0/18 1/18 17/1 1/32* 0/18 0/18 1/18** 17/ 17** * parametric failure ** pad corrosion comments on the reliability results previous results do not reveal negative effects due to the exposure of sm devices to the soldering heat, for all of the industrial smt soldering methods, in combination with the most common solders and cleaning solvents (freon, water with and without ul- trasonics). wear-out in the hast test (130 c/85%rh) is bet- ween 1100 and 1300 hours when the soldering cy- cle is repeated up to 4 times with high temperature (250-260 c) multiple wave soldering, which is con- sidered to transfer the highest thermal stress to the package body. pad corrosion is the final failure mechanism for all samples. this performance is about7-10 times better than the 2000-3000 h thb 85 c/85%rh, which is currently requested as qualification target in moisture resis- tance biased tests. therefore, the reliability of sur- face mounted devices considered in this workis high enough to meet the most stringent requirements of the professional market. no evidence of cracks in the plastic case was found in the previous evaluations. this effect (referred to also as 'pop corn' effect) is attributed to some ano- application note 3/11
malous thermal expansion of the package in the sol- dering phase, causedby water absorbed by the pla- stic encapsulation : a thermal treatment at a temperature higher than 100 c for a few hours is suggested in order to remove the absorbed water. 4 as this thermal pre-conditioning should be perfor- med shortly before soldering, a serious problem ari- ses in the assembly line. such thermal annealing is not practical when the parts are supplied in plas-tic tapes or sticks : they should be removed from the packs by the user, heat treated, and packed again with additional costs and risks (co-planarity). in this company's experience, the 'pop corn' effect can be completely avoided by controlling the frame- encapsulant interface, which is the easiest path for the water. furthermore, experience has indicated that water at that interface does change the expan- sion characteristics of the package.about five years ago, the curve of figure 3 was found in some parts (coming from lots affectedby the 'pop corn' problem) using thermo-mechanical analysis (tma). devices under test were placed between the probes of the tma transducer and their expansioncharacteristics recorded. in the first ramp (5 c/min), package expansion was much higher than the moulding compound expan- sion between 50 and 100 c ; over 100 c, it returned on the curve typical of the encapsulant. cooling down and repeating the measurement, only the lo- wer curve of figure 3 was covered. this behaviour was attributedto water having pene- trated between the frame and the plastic body, who- se expansion was responsible for the package deformation during the slow heating in tma. when the parts were soldered on the substrate, cracks could occur due to the much faster heating rate. thermal characteristics correlation between reliability and junction tempe- rature tj is known : the device lifetime is roughly halved when tj is in- creased by 10 c. mainly due to this fact, thermal dissipation is a se- cond factor which can influence smd reliability : a reduced body means worse dissipation and higher power density on the board. as careful thermal design is the key to improved re- liability, a systematic characterisation of sm packa- ges was performed, in order to study the main factorsaffecting thermal dissipationat both levels of package design and board design. in the course of this work, the need for some critical revision of the way of producing and using thermal data was evident. a point which cannotbe under-evaluatedis the choi- ce of measurement method, as will be discussed la- ter. another important point is the following : the com- mon way of specifying the junction to ambient ther- mal resistance rth(j-a) is to associate one value of rth(j-a) to each device. in the majority of data books, including this compa- ny's previous literature, little information is given on the experimental conditions used to obtain that va- lue : the dissipated power and , above all, the kind of interconnection between the package and the measurement set-up(wires, socketor board), which in some cases can become a far from negligible heat transfer element. ignoring this contribution was probably justifie with packages having a low thermal conductivity frame, such as alloy 42 or kovar. for those packages, heat spreading was limited to the silicon die and to the die pad ; thermal dissipation was little affected by the surroundings and the measurement assemblyhad little influence on the fi- nal value of rth(j-a). figure 3 : thermal expansion of so packages. the problem was solved when the possibility of con- trolling the water content was found,by means of an improved frame design and some dedicated pro- duction steps. millions of parts assembled in recent years showed no evidence of the 'pop corn' effect, without any pre- conditioning before use. the same solutions are successfully adopted for plcc packages. application note 4/11
this is not the case concerning the same packages with a copper frame, introduced a few years ago to achieve a higher power capability ; due to better thermal conductivity of the leads they are much more sensitive to external dissipating media, even- tually used for the measurement. similar statements are valid for smds and become more important on account of their reduced dimen- sions. the concept is summarised in table 7, where the thermal resistance of some dual-in-line (dip), small outline (so) and plastic leaded chip carrier (plcc) packages is given. the influence of the fra- me thermal conductibity is remarkable ; but likewise remarkable are the differences obtained for the same package, when it is connected by thin wires (and 'floating' in still air) or soldered on a pc board during the measurement. table 7 : junction to ambient thermal resistance (c/w) for dip and sm packages in different experimental conditions. power pd[w] 'floating' in air on sgs test board ratio dip 14 leads (*) alloy 42 0.25mm cu 0.25mm 0.5 0.6 156 125 138 90 1.13 1.39 so-14 leads (**) alloy 42 0.25mm cu 0.25mm 0.4 0.6 280 190 195 105 1.43 1.80 plcc-44 leads (***) cu 0.25mm 1.0 70 52 1.35 die size : (*) = 0.095 in. x 0.110 in. (**) = 0.060 in. x 0.090 in. (***) = 0.180 in. x 0.180 in. especially for so packagesthe influence of the sub- strate on thermal dissipation is noticeable. this fact can help to explain the following points : 1. the rth(j-a) values published by different smd suppliers are distributed in too wide a range (more than 70 c/w for so packages) which han- dicaps a correct thermal design. most of the dif- ference is probably due to different test boards, and the availability of standardised measure- ment methodology should help to give more ac- curate information. 2. the board lay-out contribution should be studied, in order to quantify the effect of device density : a suitable distance between two or more dissipa- ting elements can be an effective solution for im- proved reliability. 3. specification of thermal characteristics should in- clude more elements (power level,board density, package design) which cannot be summarised in one singlethermal resistance value, as was com- monly the case with alloy 42 dips. a set of experimental curves was obtained for each sm package, 2 which gives the relationship between thesefactors ; if used to feed back the boardde-sign, they should help to achieve a better thermal perfor- mance. the most significant results will be discussed here. moreover, two other factors will be considered. 1. the thermal capacitance of the package, which is significant especially in higher pin count plccs ; it delays tj increase during power tran- sients and is important in switching applications. 2. the frame design in association with a suitable board design ; a low resistance thermal path can be obtained with modified frames ; heat is then conveyed to copper areas obtained on the board and dissipated power can be increased to 2w with sos and plccs. experimental method when thermal measurements on plastic packages are performed, the first consideration is the lack of a standardmethod : at present, only draft specifica- tions 5 exist, proposed in 1986 and not yet standa- rdised. the experimental method used in this company sin- ce 1984 has anticipated these preliminary recom- mendations to some extent, as it is based on the p432 thermal test pattern (figure 4) having two npn transistors, with 10w each power capability. a sen- sing diode is placed on the thermal plateau arising when the transistors are operating in parallel and gi- ves the actual value of tj, through the calibration curve of its forward voltage vf (at constant current) vs temperature. transistor size, which is not fixed by the documents proposed for standardisation, was intentionallylimi- ted to 1000 mils 2 , in order to simulate a high power density and characterise the worst case. die size, which is found to have some influenceon thermal re- sistance when copper frame is used, is slightlysmal- ler than the die pad size and never exceeds 30000 mils 2 in larger packages, such as high pin count plccs. the measurement set-up is shown in figure 5. it is compatible with dc and ac power supply and has an accuracy better than 5%. application note 5/11
the advantages offered by the test pattern are : (i) high power capability (wider evaluation range) ; (ii) repeatable electrical characteristics (vf) and temperature coefficient (1.9mv/c) of the sen- sing element (accuracy) ; (iii) high resolution in pulsed conditions (evaluation down to 100s pulses) ; (iv) better correlation from one package to another. alloy 42 frames and copper frames were used for narrow so packages (150 mils body) ; only copper frames were considered for the others : wide so (300 mils body) and plcc packages. suitable fr-4 test boards were developed, which will be described case by case. figure 4 : test pattern p432 layout. figure 5 : measurement system. thermal characteristics in dc condi- tions thermal characteristics of the so-14 package in dc conditions are shown in figure 6. the upper curve is related to samples floating in still air and connected to 8 thin wires needed for biasing the dissipating transistors and the sensing diode of the p432 test pattern. figure 6 : rth(j-a) of so-14 package vs. power level. figure 7 : rth(j-a) of so-14 vs. on board trace area. samples soldered on the fr-4 test board shown in figure 2 have an approximately halved thermal re- sistance ; by reducing the copper pattern length of the test board, different component densities are si- mulated : thermal resistance is increased by about 30% when the track length has the minimum value. dependence of the thermal resistance on the total area of the traces connected to the package is re- presented by the curve of figure 7. it quantifies the effectivenessof the board lay-out to spread the heat and dissipate it towards the ambientand can be con- veniently used for determining the thermal resistan- ce value associated with a given board design. application note 6/11
figure 8 : rth(j-a) of so-14 with copper (sgs- thomson) and alloy 42 frame. comparison of low conductivity (alloy 42) and high conductivity (copper) frames is shown in figure 8. the data obtainedfor the different sm packages are summarised in table 8 ; the two thermal resistance values refer to the two extreme cases of a low den- sity and a high density board. table 8 : summary of junction to ambient thermal resistance in steady state power dissipation (sgs-thomson test boards) die pad size (milinches) power pd [w] rth(j-a) [ c/w] on board so-8 alloy 42 90 x 100 0.2 250-310 copper 95 x 100 0.2 160-210 so-14 alloy 42 98 x 118 0.3 200-240 copper 78 x 118 0.5 120-160 copper 98 x 125 0.7 105-145 so-16 alloy 42 98 x 118 0.3 180-215 copper 94 x 185 0.5 95-135 so-16w copper 120 x 160 0.7 90-112 so-20 copper 140 x 220 0.7 77-97 plcc-20 cu 180 x 180 0.7 90-110 plcc-44 cu 260 x 260 1.5 50-60 plcc-68 cu 425 x 425 1.5 40-46 plcc-84 cu 450 x 450 2.0 36-41 rth(j-a) values correspond to low and high board density figure 9 : qualitative tj increase for single po- wer pulse. thermal impedance in pulsed condi- tions the electrical equivalent of heat dissipation for a module formed by the active device, its package,the board and the externalambient is a chainof rc cells each having a characteristic risetime t = rc. thermal capacitance is the capability of heat accu- mulation and depends on the heat capacitance of the materials, their volume and their density. when the power is switched on, the junction tempe- rature after a time t is the result of the subsequent charge of the rc cells, according to the well known exponential relationship : d t j = rth x pd x (1 et/ t ) when the pulse length t o is an assigned value, ef- fective t j can be significantly lower than the steady state t j (figure 9) and a transient thermal resistance rth(t o ) can be defined, from the ratio between the junction temperature at the end of the pulse and the dissipated power. obviously, for shorter pulses, transient thermal re- sistance is lower and a higher power can be dissi- pated without exceeding the maximum junction temperature defined in reliability considerations. in a similar way, when pulses of the same height pd are repeated with a defined duty cycle dc and the pulse is short in comparison with the total risetime of the system, the train of pulses is seen as conti- nuous source at a mean power level : pd avg =pdxdc application note 7/11
on the other hand, the silicon die has a risetime of 1-2ms and is able to follow frequencies of some khz : junction temperature oscillates about the ave- rage value : d tj avg = rth x pd avg as qualitatively shown in figure 10. the thermal resistance corresponding to the peak of the oscillation at the equilibrium (peak thermal resi- stance) gives information on the maximum tempe- rature reached by the device and, depending on dc and pulse width, can be much lower than dc ther- mal resistance. figure 10 : qualitative tj increase for repeated power pulse. figure 11 : test board for plcc. the knowledge of thermal characteristics in the ac condition is a valid tool to reduce redundancy (and cost) in the thermal design of pulsed applications. the example is nowgiven of a high pin count plcc, which has a large thermal capacitance,due to its vo- lume and weight. temperature increase for 84 lead plccs soldered on the sm pcb5 test board(figure 11) for single pul- ses of differentlength is given in figure 12. a risetime of 50-60s is typical for this package, having a ther- mal resistance of 38 c w in steady state (see table 8). for single pulses, the effective thermal resistance is much reduced and acceptable junction temperature is observed even for high power pulses. 10w can be delivered for about 1s (9 c/w) and 5w for 10s (18 c/w). peak thermal resistance for repeated pulses, with different duty cycles, is represented in figure 13 and the above considerations are valid in this case also. figure 13 : peak transient rth for plcc-84 on the board. figure 12 : transient thermal resistance for plcc-84 on board. application note 8/11
medium power application the lack of power packages suitable for smt requi- rements (standard outline, automatic handling) is known. a simple way to achieve powerdissipation in the me- dium range (1-2w) is to transform the available si- gnal packages and modify their frame to obtain a high conduction path. in figure 14 the frame of medium power so and plcc packages is shown : some leads are connec- ted to the die pad, in order to have a low junction- to-pin thermal resistance rth(j-p). typical values of this parameter are in the range of 12-15 c/w, with a high conductivity lead frame. modification involves the internal part of the frame only, while the external dimensions of the package are not changed ; the solution offers the undoubted advantage of being compatible with existing hand- ling and testing tools. the heat produced by the ic, and conveyed exter- nally by the heat transfer leads, can be cost effecti- vely transferred to the ambient by means of dedicated copper heatsinks, integrated on the bo- ard. figure 14 : medium power so and plcc frame. in figure 15, the layout of test boards used for the thermal characterisation of medium power so-20s (with 8 heat transfer leads) and plcc-44s (with 11 heat transfer leads) is represented. the area of the integrated heatsink can be optimi- sed for cost reduction, depending on the dissipation level. in figure 16 the relationship between the rth(j-a) of the plcc (33 + 11) and the total dissipa- ting area is given. it can be noticed that, with 6-7 sq cm of substrate, the thermal resistance of plcc-44s can be decreased from 55 c/w to 40 c/w, for 1.5-2w dissipation. a similar performance is possible with the medium power sos. figure 15 : test boards for medium power so-20 and plcc-44 package. conclusions in smt, two main reliability related concerns are re- sistance to soldering heat and heat dissipation. resistance to soldering heat after extensive evaluation of devices soldered on plastic substrates by means of the three industrial soldering methods (multiple wave soldering, vapour phase and ir reflow), no reliability degradationwas found. the following soldering conditions are possible with so packaged devices : . multiple wave : t = 250 - 260 c/t = 4s (repetition allowed) . vapour phase : t = 215 c/t = 20s (repetition allowed) . infra-red : t > 210 c/t = 60s (tmax = 225 c) figure 16 : rth(j-a) of medium power plcc-44 vs. dissipating area on board. application note 9/11
no crack in the plastic case was evidenced during the above work or in the field, in recent years of pro- duction, and no thermal preconditioning was nee- ded. however, this result was obtained after optimisation of the frame design and of the produc- tion process. its extension to the totality of the pro- ducts existing on the market might be too arbitrary, but it is possible to conclude that the structure of sm packages, when associated with suitable materials and processes, is able to meet the user's require- ments. a similar evaluation is running for plcc packages and will be completed in the first half of 1988. heat dissipation some considerations have been made about the consequence of the lack of some standard evalua- tion methodology.to standardisetest chips and test boards is very important, in order to reach a better knowledge and a better information exchange. by means of an internally developed test pattern and suitable test boards, three points have been stu- died : 1. the influence of the substrate on thermal dissipa- tion, whose effect has to be taken into account much more than for insertion packages. with a properlayout it is effective in reducing thermal re- sistance. for example, dissipation of copper fra- me so package can become better than the equivalent alloy 42 dip and only 10-20% higher than the equivalent copper dip. 2. the thermal impedance, whose value is much more suitable for the thermal design of switching applications and can contribute to reduce the cost of the system. 3. thenew medium power soand plcc packages, which offer the possibility of cost-effective power dissipation in the range of 1.5-2w, still maintai- ning a standard outline. references 1. nakahara, h., 'smt expands options in japan', electronic packaging and production, vol. 26, no. 1, p. 58, january (1986). 2. sgs-thomson applicationnotes 106 to 110 on so-8, 14, 16, 16w, 20 and plcc-20, 44 (33 + 11), 68, 84. 3. peck. d. s., 'comprehensive model for humidity testing correlation', proceedings irps, p. 44 (1986). 4. fukuzawa, 1. et al, 'moisture resistance degra- dation of plastic lsi by reflow soldering', pro- ceedings irps, p. 192 (1985). 5. semi draft specifications 1377 and 1449 (1986). application note 10/11
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 11/11

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